1. Field of the Invention
This invention relates to an improved bipolar receiver and more particularly a receiver which provides relatively large complementary output voltage transitions and in one embodiment also provides a cascoded current latch.
2. Description of the Prior Art
There are many receivers and other circuits which perform level conversion, complement generation and latching functions in the prior art. Prior art proposals include the following:
U.S. Pat. No. 3,601,636 to Marsh, Jr., entitled "Single-Shot Device", discloses a single-shot device having two NAND gates which are interconnected to provide an output signal in response to an input signal. The output signal remains for a predetermined duration until the output signal of one NAND gate is applied through a delay to the other NAND gate. The delay comprises a transient network which performs an integrating function and contains a series connected resistor and a parallel connected capacitor.
U.S. Pat. No. 4,494,017 to Montegari, entitled "Complementary Decode Circuit", discloses a decode circuit which utilizes NPN and PNP transistors and performs a complete decode function in only one logic level with the no need for a true/complement input of each binary input. A first embodiment of the decoder provides an UP level output when selected. A second embodiment of the decoder provides a DOWN level output when selected. The decode circuit may be used as an address decode circuit in a memory and also portion(s) of the decode circuit may be used independently as a binary logic circuit. Also disclosed is a complementary current switch logic circuit with dual phase outputs.
U.S. Pat. No. 4,614,885 to Brosch et al., entitled "Phase Splitter With Latch", discloses a phase splitter with latch comprising a true complement generator in the form of a current switch which supplies two complementary output signals in response to an input signal. The outputs of this true complement generator are in each case connected to an associated emitter follower. The two emitter followers have identical emitter resistors which simultaneously serve as collector load resistors of two cross-coupled transistors also comprise identical but higher emitter resistors than the emitter followers. The emitters of the cross-coupled transistors are each connected to one of the two inputs of an output stage consisting of a current switch. This current switch is connected to operating voltage through a clock-controlled transistor. Upon actuation of the output stage, i.e., when transistor is on, the active emitter resistance of one of the cross-coupled transistors is pulled below the value of the emitter resistors of the emitter followers, thus causing the latch circuit to be latched as a function of the input signal.
U.S. Pat. No. 4,806,799 to Pelley et al., entitled "ECL to CMOS Translator", discloses integrated circuits which include both ECL and CMOS circuits, there is an ECL to CMOS translator which converts ECL logic levels to CMOS logic levels. To convert from ECL to CMOS levels, the ECL logic high is coupled to the base of an NPN transistor which provides a CMOS logic low. The ECL logic low is prevented from being coupled to the base of the NPN transistor. The CMOS logic high is obtained by an analogous second circuit which is responsive to a complementary ECL signal the output of which is coupled to a P channel transistor. The P channel transistor either provides the CMOS logic high output or is non-conductive.
Technical Disclosure Bulletin IBM TDB FI8-71-0254 describes a True/Complement generator having both up level and down level clamps on the collector nodes of the ECL portion of the circuit. It also features dual output emitter followers for each phase.
A brief consideration of the operation of a typical prior art bipolar receiver shown in FIG. 1 illustrates the prior art limitations for the class of bipolar receivers to which this invention is applied. Here bipolar NPN transistors T1A and T2B form an emitter coupled logic (ECL) switch. A current mirror comprised of resistor R2, transistor T3 and transistor T4 serves as a current source (sink) is for T1A and T2B. Typically, the positive supply V.sub.cc about +1.4 volts and negative supply V.sub.EE is about -2.2 volts.
Input terminal 10 is coupled to the base of emitter follower T1 which in turn is coupled to the base of transistor T1A. The base of T2B is coupled to the emitter of transistor T2 base is coupled to ground and the collectors of transistors T1A and T2B are coupled to the bases of transistors T5 and T6, respectively. Output terminal 14 replicates the input at terminal 10 and output terminal 16 replicates its complement.
In operation, with the input terminal 10 at its low state (e.g., -0.5 volts), T1 is off, T1A is off, and T2B is on, conducting a current whose magnitude is established by R2-T3-T4 current mirror. The gate of T6 is pulled down, shutting it off so that the voltage at output terminal 14 is approximately equal to V.sub.EE. Similarly, when T1A is off, the base potential of T5 rises, turning it on and the potential of terminal 16 is V.sub.cc less the drop across T5. It will be appreciated that when the input to terminal 10 goes high (e.g., +0.5 volts) T1A turns on, T2B turns off and the just described operation reverses turning on T6 and turning off T5.
Bipolar receivers of the type shown in FIG. 1 are more desirable than CMOS receivers because they have higher immunity to electrostatic discharge damage, and their more stable threshold makes them better suited to receiving small (e.g., .+-.0.5 volt) transitions. However, the output voltage transition produced by a bipolar receiver is usually limited to .about.2 volts due to saturation constraints, and cascoded current steering devices for latching of received data cannot be added for the same reason.